The invention is directed to a method for the identification of peripheral equipment within a digital communication system, particularly a message switching system, comprising a central data processor as central controller and comprising a plurality of decentralized input/output processors that are equipped with memories as subscriber and line sets and control the peripheral equipment, said decentralized input/output processors being respectively in communication with the central data processor via a peripheral interface means.
Communication systems defined in such fashion represent modularly constructed private branch exchanges having few standard interfaces that are built in a great variety of system sizes corresponding to the jobs to be met. These message switching systems as private branch exchanges can be connected both to public networks and public services--telephone network, teletex network, etc.--as well as to private networks--sub-systems, tie trunk lines. Analog and digital terminal equipment are provided as subscriber terminals. Via corresponding interfaces, there is also an additional possibility of connecting external equipment such as printers, operations-related terminals (PC), etc.
The system architecture of the different communications systems is uniformly structured in three levels: Periphery, decentralized input/output processors and central processor.
Accordingly, assemblies as interfaces to the connected terminal equipment and lines (subscriber sets, line sets) and assemblies for call setup such as signalling equipment, transmitters and receivers belong to the periphery. The chronologically critical handling of the periphery is thereby assumed by the decentralized input/output processors, whereby the number of peripheral equipment or, respectively, the number of connector sets for every input/output processor is limited dependent on the maximum, overall data set to be processed. Among other things, the input/output processors are thus provided for the control of the standard interfaces and local busses, of the digit interpretation, of the connection of tone clocks and call clocks and of dependability-oriented displays. The central data processor, by contrast, coordinates the control of all equipment present in the communication system via appropriate bus connections. The reset logic and dependability-oriented events are also centrally controlled by the central data processor.
The interface between the decentralized input/output processor and the central data processor is enabled by a memory that can be written and read out by both processors. The control of this memory usually ensues on the basis of the operating system that is employed.